PCIE Core

The BackPlane always contains one core responsible for interacting with the computer. In newer, PCI-E cards, it is connected via the PCI-E Core. This core has a Core ID of 0x820.

PCI-E Core Registers

Offset	Size (bytes)	Meaning
0xC	4	Bist(?) Status
0x28	4	Backplane to PCI-E Mailbox
0x100	4	Backplane to PCI-E Translation 0 (sbtopcie0)
0x104	4	Backplane to PCI-E Translation 1 (sbtopcie1)
0x108	4	Backplane to PCI-E Translation 2 (sbtopcie2)
0x120	4	PCI-E Configuration Space: Address
0x124	4	PCI-E Configuration Space: Data
0x128	4	MDIO Access: Control
0x12C	4	MDIO Access: Data
0x130	4	PCI-E PHY/DLLP/TLP Register Access: Address
0x134	4	PCI-E PHY/DLLP/TLP Register Access: Data

Reading and writing PCI-E Configuration Space or PCI-E Registers

First, write the register offset to the control register (0x120 for PCI-E Configuration Registers or 0x130 for PCI-E Registers), then either read or write the the associated data register.

PCI-E Configuration Space Registers

PCI-E Registers

TLP Diagnostic Registers

Offset	Size	Usage
0x0004	4	TLP Workarounds Register

DLLP Diagnostic Registers

Offset	Size	Usage
0x0100	4	Link Control Register

PHY Diagnostic Registers

MDIO Access

MDIO Control Register Usage

Bitmask	Usage
0x007F	MDIO Clock Divsor
0x0080	Enable/Disable Preamble Sequence
0x0100	MDIO Transaction Complete

MDIO SERDES Devices

Address	Device
0x1F	SERDES RX Device

SERDES RX Device Registers

Offset	Usage
2	RX Timer
6	CDR
7	CDR BW

Write to MDIO Slaves

Write 0x82 (Enable Preamble Sequence bitwise OR'd with a divisor value of 2) to the MDIO Control Register
Prepare the MDIO data packet with the Start of Transaction bit set, the Write Transaction bit set and the Turnaround bit set, finally, fill in the addresses and data as needed
Write the MDIO data packet to the MDIO Data Register
Delay for 10 uSec
Check every 1 mSec for 10 mSec to see if the MDIO Transaction Complete bit is set in the MDIO Control Register
Once the transaction is completed or fails, write 0 to the MDIO Control register

MDIO Data Packet Format

Bits	30	29	28	27-22	21-18	17	15 - 0
Usage	Start of Transaction	Read Transaction	Write Transaction	Device Address	Register	Turnaround	Data